Is it possible to use "int unsigned" from SystemVerilog in iverilog?

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Yes, it is possible to use "int unsigned" from SystemVerilog in iverilog. Iverilog supports SystemVerilog data types, including "int unsigned". However, it is important to note that not all SystemVerilog features are supported by iverilog, so it is important to check the documentation and compatibility issues before using SystemVerilog constructs in iverilog.